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  <table class="topTitle">
   <tr>
    <td class="l">ram_wr</td>
    <td class="r">ram_wr
     <br/>1.0
     <br/>
    </td>
   </tr>
  </table>
  <table class="blueBar">
   <tr>
    <td class="l">2012.11.22.10:12:02</td>
    <td class="r">Generation Report</td>
   </tr>
  </table>
  <table class="items">
   <tr>
    <td class="label">Output Directory</td>
    <td class="mono">Z:/work/All_in_one/</td>
   </tr>
   <tr>
    <td class="label">Files</td>
    <td class="mono">Z:/work/All_in_one/ram_wr/synthesis/ram_wr.v (3695 bytes VERILOG)
     <br/>
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/ram_wr_onchip_memory2_0.hex (12253 bytes HEX)
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/ram_wr_onchip_memory2_0.v (4019 bytes VERILOG)
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/ram_wr_onchip_memory2_1.hex (12253 bytes HEX)
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/ram_wr_onchip_memory2_1.v (4019 bytes VERILOG)
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/altera_reset_controller.v (3592 bytes VERILOG)
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/altera_reset_synchronizer.v (3564 bytes VERILOG)
     <br/>Z:/work/All_in_one/ram_wr/synthesis/submodules/altera_reset_controller.sdc (1179 bytes SDC)
     <br/>
    </td>
   </tr>
   <tr>
    <td class="label">Instantiations</td>
    <td class="mono">
     <table class="grid">
      <tr>
       <td><b>ram_wr</b>
        <br/>ram_wr v1.0</td>
       <td><b>ram_wr_onchip_memory2_0</b> as onchip_memory2_0
        <br/><b>ram_wr_onchip_memory2_1</b> as onchip_memory2_1
        <br/><b>altera_reset_controller</b> as rst_controller
        <br/>
       </td>
      </tr>
      <tr>
       <td><b>ram_wr_onchip_memory2_0</b>
        <br/>altera_avalon_onchip_memory2 v11.0</td>
       <td></td>
      </tr>
      <tr>
       <td><b>ram_wr_onchip_memory2_1</b>
        <br/>altera_avalon_onchip_memory2 v11.0</td>
       <td></td>
      </tr>
      <tr>
       <td><b>altera_reset_controller</b>
        <br/>altera_reset_controller v11.0</td>
       <td></td>
      </tr>
     </table>
    </td>
   </tr>
  </table>
  <div style="width:100% ;  height:10px"> </div>
  <div class="label">Generation Messages</div>
  <div style="white-space:pre ; font-family:courier">2012.11.22.10:11:45 [Info] ram_wr.onchip_memory2_0: Memory will be initialized from onchip_memory2_0.hex
2012.11.22.10:11:45 [Info] ram_wr.onchip_memory2_1: Memory will be initialized from onchip_memory2_1.hex
2012.11.22.10:11:45 [Info] ram_wr: Generating <b>ram_wr</b> "<b>ram_wr</b>" for QUARTUS_SYNTH
2012.11.22.10:11:45 [Debug] ram_wr: queue size: 0 starting:ram_wr "ram_wr"
2012.11.22.10:11:45 [Debug] Transform: PipelineBridgeSwap
2012.11.22.10:11:45 [Info] pipeline_bridge_swap_transform: After transform: <b>3</b> modules, <b>4</b> connections
2012.11.22.10:11:45 [Debug] Transform: ClockCrossingBridgeSwap
2012.11.22.10:11:45 [Debug] Transform: QsysBetaIPSwap
2012.11.22.10:11:45 [Debug] Transform: CustomInstructionTransform
2012.11.22.10:11:45 [Info] No custom instruction connections, skipping transform 
2012.11.22.10:11:45 [Debug] Transform: TristateConduitUpgradeTransform
2012.11.22.10:11:45 [Debug] Transform: TranslatorTransform
2012.11.22.10:11:45 [Info] No Avalon connections, skipping transform 
2012.11.22.10:11:45 [Debug] Transform: DomainTransform
2012.11.22.10:11:45 [Debug] Transform: RouterTransform
2012.11.22.10:11:45 [Debug] Transform: TrafficLimiterTransform
2012.11.22.10:11:45 [Debug] Transform: BurstTransform
2012.11.22.10:11:45 [Debug] Transform: ResetAdaptation
2012.11.22.10:11:45 [Progress] min: 0
2012.11.22.10:11:45 [Progress] max: 1
2012.11.22.10:11:45 [Progress] current: 1
2012.11.22.10:11:45 [Info] reset_adaptation_transform: After transform: <b>4</b> modules, <b>6</b> connections
2012.11.22.10:11:45 [Debug] Transform: NetworkToSwitchTransform
2012.11.22.10:11:45 [Debug] Transform: WidthTransform
2012.11.22.10:11:46 [Debug] Transform: RouterTableTransform
2012.11.22.10:11:46 [Debug] Transform: ClockCrossingTransform
2012.11.22.10:11:46 [Debug] Transform: PipelineTransform
2012.11.22.10:11:46 [Debug] Transform: TrafficLimiterUpdateTransform
2012.11.22.10:11:46 [Debug] Transform: InterruptMapperTransform
2012.11.22.10:11:46 [Debug] Transform: InterruptSyncTransform
2012.11.22.10:11:46 [Debug] Transform: InterruptFanoutTransform
2012.11.22.10:11:46 [Debug] ram_wr: "<b>ram_wr</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/ram_wr_onchip_memory2_0</b>"
2012.11.22.10:11:46 [Debug] ram_wr: "<b>ram_wr</b>" reuses <b>altera_avalon_onchip_memory2</b> "<b>submodules/ram_wr_onchip_memory2_1</b>"
2012.11.22.10:11:46 [Debug] ram_wr: "<b>ram_wr</b>" reuses <b>altera_reset_controller</b> "<b>submodules/altera_reset_controller</b>"
2012.11.22.10:11:46 [Debug] ram_wr: queue size: 2 starting:altera_avalon_onchip_memory2 "submodules/ram_wr_onchip_memory2_0"
2012.11.22.10:11:46 [Info] Starting classic module elaboration.
2012.11.22.10:11:48 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder  -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0003_sopclgen  --no_splash --refresh C:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip"
2012.11.22.10:11:50 [Info] Finished elaborating classic module.
2012.11.22.10:11:50 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0003_sopclgen/yysystem.ptf
2012.11.22.10:11:50 [Info] Running sopc_builder...
2012.11.22.10:11:51 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder  -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0003_sopclgen  --generate C:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0003_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip"
2012.11.22.10:11:53 [Progress] No .sopc_builder configuration file(!)
2012.11.22.10:11:53 [Progress] .
2012.11.22.10:11:54 [Progress] # 2012.11.22 11:11:53 (*) Success: sopc_builder finished.
2012.11.22.10:11:54 [Info] onchip_memory2_0: "<b>ram_wr</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>onchip_memory2_0</b>"
2012.11.22.10:11:54 [Debug] ram_wr: queue size: 1 starting:altera_avalon_onchip_memory2 "submodules/ram_wr_onchip_memory2_1"
2012.11.22.10:11:54 [Info] Starting classic module elaboration.
2012.11.22.10:11:56 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder  -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0004_sopclgen  --no_splash --refresh C:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip"
2012.11.22.10:11:57 [Info] Finished elaborating classic module.
2012.11.22.10:11:57 [Progress] Executing: C:/altera/11.0/quartus//sopc_builder/bin/sopc_builder --classic --generate C:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0004_sopclgen/yysystem.ptf
2012.11.22.10:11:57 [Info] Running sopc_builder...
2012.11.22.10:11:59 [Progress] "c:/altera/11.0/quartus/bin/jre/bin/java.exe" -Xmx512M -classpath "c:/altera/11.0/quartus/sopc_builder/bin/sopc_builder.jar;c:/altera/11.0/quartus/sopc_builder/bin/PinAssigner.jar;c:/altera/11.0/quartus/sopc_builder/bin/sopc_wizard.jar;c:/altera/11.0/quartus/sopc_builder/bin/jptf.jar" sopc_builder.sopc_builder  -d"c:/altera/11.0/quartus/sopc_builder" -notalkback=1 -projectnameyysystem.qpf -projectpathC:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0004_sopclgen  --generate C:/Users/RAS/AppData/Local/Temp/alt5666_4297341041825317909.dir/0004_sopclgen/yysystem.v --quartus_dir="c:/altera/11.0/quartus" --sopc_perl="c:/altera/11.0/quartus/bin/perl" --sopc_lib_path="++c:/altera/11.0/quartus/../ip/altera/sopc_builder_ip+c:/altera/11.0/quartus/../ip/altera/nios2_ip"
2012.11.22.10:12:00 [Progress] No .sopc_builder configuration file(!)
2012.11.22.10:12:01 [Progress] .
2012.11.22.10:12:01 [Progress] # 2012.11.22 11:12:01 (*) Success: sopc_builder finished.
2012.11.22.10:12:02 [Info] onchip_memory2_1: "<b>ram_wr</b>" instantiated <b>altera_avalon_onchip_memory2</b> "<b>onchip_memory2_1</b>"
2012.11.22.10:12:02 [Debug] ram_wr: queue size: 0 starting:altera_reset_controller "submodules/altera_reset_controller"
2012.11.22.10:12:02 [Info] rst_controller: "<b>ram_wr</b>" instantiated <b>altera_reset_controller</b> "<b>rst_controller</b>"
2012.11.22.10:12:02 [Info] ram_wr: Done <b>ram_wr</b>" with 4 modules, 8 files, 44574 bytes
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